To increase the cell area of a static random access memory (SRAM) and to increase the standby power in response to miniaturization, research for utilizing not the SRAM which has been conventionally used, but a nonvolatile, large-capacity and high-speed next-generation nonvolatile semiconductor memory such as a spin-transfer-torque magnetic random access memory (STT-MRAM) as a cache memory of the processor have been advanced.
For example, since STT-MRAM is capable of storing data in a nonvolatile state, STT-MRAM can reduce the standby power more remarkably than a conventional SRAM. In addition, the cell area of the STT-MRAM is smaller than the cell area of the SRAM. For example, the cell area of the STT-MRAM for storing data per bit needs only to be one fourth to one tenth of that of the SRAM. Furthermore, the STT-MRAM can execute high-speed read/write operations, similarly to the SRAM.
Thus, the next-generation nonvolatile semiconductor memory is expected to contribute to the enhancement in performance of the processor.
In contrast, the next-generation nonvolatile semiconductor memory requires a comparatively large write current when, for example, data is written in the memory cell. For this reason, the write needs to be executed with a write pulse width as short as possible, to reduce the power consumption at the write.
In general, however, the write property (write pulse width necessary for the write) of the memory cell is varied. In consideration of this, the write pulse width needs to correspond to the memory cell having the worst property and, as a result, sufficient reduction in the write pulse width and lower power consumption are difficult.